Home, sweet home

The trip back from Taipei works like this: I hop on a plane from Taipei to Los Angeles at around 11:55PM Thursday night. The flight itself takes about 11 hours (it's faster coming back than it is going). Then, I've got a couple of hours to kill in LAX after which I board yet another plane, this time departing for Charlotte, NC - around 4 hours there. Finally I take my last flight, a 23 minute flight (with around 30 minutes of waiting to take off) from Charlotte to Raleigh. No matter how you slice it, by the end of the trip there's nothing you want more than a shower. So I got home yesterday and did just that.

Computex was a lot of fun if you couldn't tell by the excitement in the articles we posted or my updates from the trip. I was honestly quite worried that I was burnt out at the end of my four years at State; in a sense I was, but I was burnt out from college and not from the work I enjoy doing so very much. Unfortunately, I think I tried to get back into the groove a little too fast and I ended up getting sick in Taipei. I'm still recovering, feeling a bit better, but still fighting off my Computex Cold.

I have this issue when it comes to traveling to Taiwan, it takes me around 2 weeks to get used to east coast time again. Taiwan time is a full 12 hours behind from the local time here in NC, meaning it really messes with your mind. I've tried just about everything to get adjusted quickly to NC time but nothing's ever worked (hence why I'm up at 4:40AM typing out this blog). I took some NyQuil for my cold so hopefully that'll kick in soon and put me to sleep for a bit.

I know I said the storage review would be posted last week, well in reality it was - you just can't read it :) If you couldn't tell, we had a ton of coverage/articles go up last week and I didn't want them competing even more with one another for attention. The new HDD test suite and first article based around it goes live on Monday. It was fun to write, and I hope you all enjoy it.

One thing that I would like you all to pay particular attention to is a request I have in the article. In order to build up a good library of HDD reviews I'm going to ask for your help in deciding what drives you'd like us to review next. So every week I'd like you to email me your requests for HDD reviews and I'll do my best to satisfy them. Obviously I'd wait until this review goes live before putting in your requests, so get ready to email me starting Monday.

I'm finally working on my Dothan article, which I'm hoping to also have done for next week (although it may get published during the following week depending on schedules). I spent a bit of time talking to an Intel exec about future microarchitecture direction for desktop processors, but I could not get a straight answer as far as if we're going to see a deeper pipelined architecture, or something more conservative.

Honestly, if I were to make a guess, I'd say that we shouldn't expect a dramatic reduction in pipeline depth for Intel's next microprocessor architecture; in fact, I wouldn't expect a reduction in pipeline depth at all. That being said, I wouldn't expect a doubling of the depth as has been Intel's tradition as of late. I'd expect to see features like micro-ops fusion and potentially a more power-aware cache pulled from Banias/Dothan. I would also expect to see more power saving technology brought into the chipset, again just like the Pentium M platform. If Intel does indeed continue with a very deep pipelined architecture then you can also expect things like the trace cache to stay. Oh and multi-core is a definite reality.

I caught wind of some interesting information about Tejas, or what it was supposed to be (rumor is that it has been canceled in favor of a dual core version of the P4). Tejas was supposedly a tweaked 90nm P4 with, among other changes, twice the ALU throughput of Prescott. Tejas was also supposed to be a single core. The increased ALU throughput, I'm guessing, would come through the use of 32-bit ALUs as opposed to the current 16-bit ALUs used in the P4....which brings me to my next question: although I know Northwood used 16-bit ALUs, did Prescott migrate to 32-bit ALUs? Derek and I have been debating this back and forth, I say no, he says yes. Intel never got back to us with a real answer on whether the ALU was modified from Northwood (they never said it was different and they never said it wasn't). If Intel kept the same 16-bit ALUs from Northwood, it would mean that 64-bit integer performance would suffer a penalty because data would have to be fed back to the ALUs a second time in order to complete a single 64-bit operation (assuming two of the P4's 16-bit ALUs are used for a single operation). Intel has had a 32-bit P4 compatible ALU read for quite a while, which I saw about two years ago running at 10GHz (5GHz double pumped). If Intel has already migrated to their 32-bit ALU then the 64-bit performance discussion isn't as important. I'll send some emails this weekend to see if I can't get a straight answer now that Prescott has been out for a while.

I think I feel the NyQuil kicking in, so it's off to bed I go.

Goodnight all.